FIG. 1 schematically represents a conventional flash type electrically-erasable programmable read-only-memory (EEPROM) integrated circuit 10. The EEPROM 10 typically is manufactured on a silicon substrate 12 having a high voltage peripheral circuit region 14, standard peripheral circuit region 16, and core region 18 formed thereon. As is known with such conventional flash EEPROMs, the core region 18 is made up of an array of core transistors making up floating gate memory devices. The peripheral circuit region 16 typically includes MOS-type low voltage transistors such as those used to form a row decoder which is connected to the core array. The high voltage peripheral circuit region 14 typically includes MOS-type high voltage transistors designed for use in programming and erase operations.
The different types of transistors have different requirements insofar as operation, applied voltages, etc. Accordingly, oftentimes it is desirable to optimize the transistors based on how the transistors will be utilized in the device. For example, it may be desirable to customize the voltage junctions experienced by the high voltage and/or low voltage transistors as compared to the core transistors. In the past, this would require the use of one or more additional masks as part of an implant step. The additional mask(s) added to the production cost and time associated with the manufacture of the device.
In view of the aforementioned shortcomings, there exists a strong need in the art for a process by which the voltage junctions for the high and/or low transistors may be optimized without requiring an additional masking step.